continue.... root cause...

[moliam]

@paboldin CPU translate a virtual address through MMU unit that would resolve where the virtual memory is in the physical memory space(cache, main memory, etc) and check the privilege. I suppose that these two action should always be carried out simultaneously. So as you said in the scenario of L1 cache fetch, only data value is cached in L1 while the privilege information is not cached? If not cached, then it makes sense that a racing situation can happen. If cached, there should be another deep reason for meltdown.

[moliam]

anybody there..... ?

[paboldin]

I suppose that these two action should always be carried out simultaneously

It does not matter how you think it should be done.

It is done the other way in real hardware hence the leak.