Consider adding Verilog style `+:` (and possibly `-:`) slice operator(s)

[ChrisDodd]

P4's slicing syntax is derived from Verilog, using expressions like:

• foo[7:0] -- extract the bottom 8 bits of foo
• bar[31:24] -- extract 8 bits bar (3rd byte from lsb)

As with Verilog, the indexes are required to be constants, so as to not incur excessive cost in hardware. This is also very important for typechecking as the size of a bitslice is always a constant and can be readily determined.

Recent versions of Verilog have added a syntax allowing limited variable slices with fixed size. A slice of the form bitvec [ expr +: const ] is equivalent to bitvec [ expr + const - 1 : expr ] but allows expr to be any expression (not just a constant). The resulting slice can still be typechecked easily (since const is required to be constant, the size of the result is constant).

This could be considered as syntactic sugar -- the expression bv [ e +: k ] is equivalent to (bv >> e)[k-1:0] in semantics, and could be converted to that. However, on some targets it may actually be easier to deal with the +: form rather than having a separate shift and slice.

Personnel

• [x] Owner: @ChrisDodd
• [x] Supporters: @jafingerhut

Design

• [x] Document: Description above, plus text in PR for spec, should be sufficient.

Implementation

• [x] p4-spec: https://github.com/p4lang/p4-spec/pull/1316
• [x] p4c: https://github.com/p4lang/p4c/pull/4917

Process

• [ ] LDWG discussed:
• [ ] LDWG approved:
• [ ] Merged into p4-spec:
• [X] Merged into p4c:

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