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oskirby
Logicbone ECP5 Development Board
It seems that there are three ways in which the ECP5 can reset itself in order to handle multi-boot images: - VCC, VCCAUX and VCCIO8 rise above their POR thresholds....
Hello I am a FPGA developer If you want to add your board to IceStudio you only have to send me one board, and I am glad to include the...
The list of things yet to be tested on the prototype boards before we should start looking into the next revision - [x] Micro-SD card slot. - [x] Downstream-Facing USB...
The 25MHz crystal used to generate the PCIe and DDR3 clocks is coprime with the desired frequency needed for the USB bootloader (48MHz) which leads to some awkwardness in the...
MDIO is an open drain bus, and the FPGA's internal pullup is too weak to drive the bus correctly. Adding a 5k pullup allows us to detect and read the...
While trying to synthesize using LiteDram, we get an error that pin DDR3_DM1 is not located in the same DQS group as the rest of the high DQS bank (it...
This issue is mostly just to keep a list of parts that we might want to change out if we get a chance. | Designators | Part | Issue |------------------|--------------------|----------...
The MxL7704 datasheet leaves the purpose of the 5VSYS pin a bit ambiguous as to whether it is internally connected to VIN, or whether it's requires an external RC filter...
It seems that there is an discrepancy in the Beaglebone Black reference manual, and the schematic. The SRM states that P8 pins 11 through 21 are used for the eMMC...