Output Directory Changes

[DaleDantis]

The new Output File Structure is:-

Virtual-FPGA-Lab
   -> out
        -> "Board"
              -> "Design File"
                    -> Dependencies
                    -> Output

Board:- Any of the current implemented Boards Design File:- Any example file

Also added support for the Nexys-A7 100T

Parameterized the directories of the run.tcl script