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[XLA:CPU] Support limiting LLVM codegen in Aarch64 and other new x86 instructions
PR https://github.com/openxla/xla/pull/17722 supports limiting the CPU ISA that LLVM will codegen. It currently only supports x86 ISAs from SSE4_2 up to AMX_FP16 and imposes a strict ordering (SSE4_2 < AVX < ... < AMX_FP16). We should
- Add Aarch64 support too.
- Investigate if we need to support AVX10 and it would go in the mix with other x86 instructions.