Possible to get the Core Generator project for the ZTEX source project?

[plj567]

I'm trying to port the FPGA part to other FPGA boards and it would be very helpful to have the Xilinx Core Generator project to be able to build the bit files and modify for other targets, I have searched and unable to locate these files, are they available somewhere? Or can be made available?

Regards, Peter

[solardiz]

Hi @Apingis! Long time no talk. Are you around and available to comment on this request, please? Thank you!

[plj567]

Hello,

I generated the FIFO-Cores, I think ok, but missing modules "rd_clk" and "wr_clk"

Regards, Peter

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From: Solar Designer @.> Sent: Wednesday, March 20, 2024 8:28 PM To: openwall/john @.> Cc: plj567 @.>; Author @.> Subject: Re: [openwall/john] Possible to get the Core Generator project for the ZTEX source project? (Issue #5454)

Hi @Apingishttps://github.com/Apingis! Long time no talk. Are you around and available to comment on this request, please? Thank you!

— Reply to this email directly, view it on GitHubhttps://github.com/openwall/john/issues/5454#issuecomment-2010456378, or unsubscribehttps://github.com/notifications/unsubscribe-auth/AM2W3GMIEMVCX5KQ6R52D5TYZHPOBAVCNFSM6AAAAABFACYID6VHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDAMJQGQ2TMMZXHA. You are receiving this because you authored the thread.Message ID: @.***>

[plj567]

I've figured that the rd_clk and wr_clk must be the FIFO clocks, I try figure out the rest

[solardiz]

That's great @plj567. It doesn't look like we're going to hear from @Apingis here, so maybe once you figure things out you'd add a documentation file on your findings, to help others possibly get into this as well?

What other FPGA boards are you porting to? What do you intend to do with the host and communications and firmware code, which is now specific to ZTEX's usage of USB? Is your port intended to be part of JtR at all, or a separate project? Thank you!

[plj567]

I'm trying to get it to work on two other boards at the moment, not sure if it's worth the effort which is why I'm investigating some other sha256 & sha512 sources, if I complete it I will update and provide the board information as well

[solardiz]

Out of the algorithms we support on FPGA, it's bcrypt and descrypt where FPGAs are most competitive vs. GPUs. We also have some algorithms based on SHA-2 to allow such reuse of the hardware as well, but we assume the reason someone would acquire FPGAs is for bcrypt and descrypt. Your focus on SHA-2 suggests your use case is different. You'd have to have larger FPGAs at low cost for doing solely SHA-2 on them to be worthwhile, and that feels unlikely.

[plj567]

There are a few low cost FPGA's available, where it also fits, not so many cores though, which is the one's I'm trying to implement the code for, I'll let you know ow it goes.

[agoora]

Hi plj567, what are the FPGA boards for which you want to implement the code?

[solardiz]

Hi @plj567! Any update on your project?

[solardiz]

I'm closing this for lack of actionable tasks for us and lack of activity by @plj567, but please feel free to add comments.