orpsoc-cores
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openrisc
Core description files for FuseSoC
I can't build atlys core with ise 13.7. Output snippet I think is relevant: WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router...
Any special reason why there is no Verilator test bench for the 'vscale-generic' system, as there is for the 'or1200-generic' system (or1200-generic/bench/verilator/tb.cpp)? Is there a way to simulate a system...
I can not get 'or1200-generic' to work with Verilator after an update. If complains about: ‘class Vorpsoc_top’ has no member named ‘v’ Keep in mind that the lines of code...
How can I use more than one instance of the mor1kx simulator at the same time, and still be able to kill the instance that is giving me problems (e.g.,...
The core [wb_to_avalon_bridge](https://github.com/openrisc/orpsoc-cores/blob/master/cores/wb_avalon_bridge/verilog/wb_to_avalon_bridge.v) doesn't work when the burst support is not selected - there is no assignment for the wb_ack_o signal.
Default FuseSoC core points to https://github.com/skristiansson/wb_sdram_ctrl/commit/07eb97fc4afa5ca7bd6c17e88a5bb02474480808 , but the actual version of [wb_sdram_ctrl](https://github.com/skristiansson/wb_sdram_ctrl/) has two commits ahead. [diff](https://github.com/skristiansson/wb_sdram_ctrl/compare/07eb97fc4afa5ca7bd6c17e88a5bb02474480808...master) ``` [1;37mINFO: Running /fusesoc/orpsoc-cores/cores/elf-loader/check_libelf.sh[0m [1;31mERROR: Failed to build simulation model[0m [1;31mERROR: Failed...
I am trying to add the top level in a quartus project but many hdl files are missing from the core dir that the top level calls out.
I couldn't find pin assignment of JTAG_TAP for de0_nano from orpsoc-cores/systems/de0_nano/data/pinmap.tcl. Does that mean I couldn't use OpenOCD to write program to RAM via JTAG? This seems to explain the...
Plusargs section has been removed on some cores but not for all. Is it because some users use old versions of fusesoc or this sections can be cleaned everywhere ?
I have successfully built the SOC on a de0_nano with FuseSOC, but is there any API for how to use the various cores that come with the default build? I...