[BUG] Improper setting of `fcsr` flag after executing `feq.s` on an invalid NaN-boxed value

[riscv914]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

Based on the RISC-V ISA specification, Executing Single-Precision Floating-Point FEQ by invalid NaN-boxed inputs (a value that most significant 32 bits are not set to 1) performs a quiet comparison: it only sets the invalid operation exception flag (NV flag on fcsr) if either input is a signaling NaN. However, on CVA6, the flag is not set.

Execute the following instruction:

int main(void){
    asm volatile ("lui  t0, 0x8a1ec");
    asm volatile ("fcvt.d.w ft5, t0"); 
    asm volatile ("feq.s  t0, ft5, ft5");
    asm volatile ("csrr     t1, fcsr"); // t1=0x0000000000000000
}

- Spike version: `1.1.1-dev`
- version: `CVA6 commit: f974e105bf88cf81c32f55789b0baab4fe4d16c9`
- OS: `CentOS Linux release 7.9.2009 kernel: 5.15.0-78-generic`
- Simulator: `VCS_2023`

[JeanRochCoulon]

CVA6 uses FPU coming from CVFPU repository. To maximise the support, I advise you to post this github issue in CVFPU repository and close this current issue. Same comment for your others git issues related to FPU.

[riscv914]

@JeanRochCoulon Thank you for clarification, I will submit the issues there also.