Request for Performant XP10 SW Library

[lionelbella]

Looking for updates regarding the availability of a performant XP10 SW Library that was referenced in the OCP Zipline presentation back in 2019.

[michaelgmcintyre]

Hi Lionelbella,

While we had originally considered releasing a SW XP10 performant library, we currently have no plans to release such a library.

Thanks, Michael

[rajeshrv2020]

Hi @michaelgmcintyre Is there any drivers or libraries available as open source for this IP to be run on linux operating system. If we add this IP in an SoC, how do we access this IP ? Do we need to write our own drivers ?

Thanks Rajesh

[rajeshrv2020]

Also, is there a software golden model available to compare the compressed data in the test bench ? I see only the vectors being replayed in the test bench.

[michaelgmcintyre]

Hi rajeshrv2020,

We do not have Linux drivers available for this project. The intent was to provide the RTL and related collateral. Also, we do not have a software model, just the test bench.

Thanks, Michael

[rajeshrv2020]

Hi Micheal, Thanks for the your response. If I take this IP to Zynq FPGA and interface with ARM Core, how do I test this IP. Is there any basic drivers available or the expectation is that I need to write my own drivers to this.

Also, Is there any memory list which needs to be replaced by tech macros when I take it to FPGA or ASIC ?

Also, I didnot find much information about ENA_BMIC verilog macro apart from the following line. Can you please provide some info on this ?

BIMC | Built-In-Memory ControllerThis is a BRCM standard ECC controller which is used to provide a harness around internal SRAMs. It can monitor ECC errors as well as inject errors for test. It functions as a serial daisy chain that connects memories in a block to a standard top-level controller.
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