Explicitly declare datatype of ports in wb_intercon.v

[ukekp]

Hi,

I have run into a problem when compiling the veerwolf EL2 project in Intel Quartus Prime Pro. It will complain that the input and output ports of wb_intercon.v do not have explicit datatypes and will not pass synthesis. I think it's because I am using default_nettype none in the top-level module.

Wouldn't it be more "correct" to be explicit with the datatypes of the ports anyway?

[olofk]

Yes, you are right. This was fixed in version 1.4.0 of wb_intercon, but VeeRwolf still uses an older version of wb_intercon. We should update VeeRwolf to use a newer version. This breaks some naming though, so there is a bit more work to be done.