fusesoc
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olofk
Package manager and build abstraction tool for FPGA/ASIC development
Hello. I have a question about section "env". It have type Dict of [String] and I write core as example below ``` scripts : memory : cmd : [/bin/sh, firmware.sh]...
Hi, I like to generate coverage information for a core with ghdl (gcc backend). For this i need to add these options: `-Wc,-fprofile-arcs -Wc,-ftest-coverage -Wl,-lgcov`during make phase (ghdl -m) but...
With these example core files: [osvvm.zip](https://github.com/olofk/fusesoc/files/8541446/osvvm.zip) It seems if you for example try to set your dependancy to be >= 2020.05, only 2021.10 will be pulled. (and not 2022.01 or...
Hello, I did set some cores to cachable = false in the provider section having them downloaded from git everytime. In fusesoc list-cores they are seen as outdated (as expected)...
In my humble opinion it would be nice, if fusesoc could provide `fmt` command to format single `.core` file or all `.core` files under working directory if path to a...
Hello, There is a generic value in my VHLD design that I want to set by sending an argument value to the backend each time I run the simulation (each...
To bring in the core with generator one needs to artificially add fileset like this: ```yaml filesets: agwb_dep: depend: - wzab::addr_gen_wb generate: smx_tester: generator: addr_gen_wb parameters: infile: ../top_3_feb_c.xml targets: default:...
Original request: Make parameters (e.g. vlogdefine/vlogparam) available as use flag, to be able to do something like `depend: vlogdefine_SYNTHESIS ? corp:lib:synthesislib`. EDIT: Making flags available as parameters is easier and...
FuseSoC 2.0 (with dropped support for CAPI1) should had been out for a while already, so let's list the things remaining to get this released. Writing the items I think...
I need support for Project Mistral for my chameleon96 and Terasic Sockit Altera Cyclone V boards A blinky example done with project mistral is done here https://github.com/kprasadvnsi/mistral-CV96-blinky
