fusesoc
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olofk
Package manager and build abstraction tool for FPGA/ASIC development
Fusesoc file: ``` CAPI=2: name: core_rtl:common:sync_fifo_1c_rw:1.0.0 description: common rtl IP for synchronous Fifo, 1 clock and RW filesets: fs_rtl: files: - vlog/sync_fifo_1c_rw.sv file_type: systemVerilogSource fs_syn_yosys: files: - yosys.tcl: {file_type: tclSource,...
A complex system might require different versions of an IP in different modules. Is there a mechanism which renames modules (and probably packages, macros, functions...) to avoid name clashing?
The CAPI 2 format supports the conditional inclusion as follows: ``` hooks: post_build: - "target_chip_AA ? (generate_mcs_AA)" - "target_chip_BB ? (generate_mcs_BB)" - post_build_script ``` This is a simple example of...
I was making a core file for FuseSoc icm with ghdl for the neorv32. Since the neorv32 makes use of the library called "neorv32" the core file required a "logical_name:...
Adds a clean flag that explicitly cleans (deletes) the build directory when using the flow API.
Fixes #673 The issue was caused by 90500180872ed26c3bee2c41c50be5ff0b49c2b4 I also checked, that this fix does not break #616 again
Hi there, I wonder how to mark `.sv` files as library file in `.core` for VCS, which is as same as `-v path/to/file` in `.f` files list, and the VCS...
Hello developers and users! The Synopsis Spyglass backend (formerly Atrenta) is outdated. The supported fields are missing some newer options such as `set_goal_option`, ` current_goal`, `current_methodology`. I am currently using...
This might be temporary but highlights the issues surrounding not pinning a dependency to a particular version. The latest update to simplesat is broken and means pip installing fusesoc fails....
