fusesoc
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olofk
Package manager and build abstraction tool for FPGA/ASIC development
Im using systemrdl to implement my cores CSRs, with a generator that consumes a rdl file and compiles it to systemverilog files and thats working fine. Now lets say I...
Hi, I'm trying to find a way to set Vivado parameters using the core file (for example synthesis strategy). I can't seem to wrap my head around it - any...
Hello, I cloned repository `https://github.com/olofk/de0_nano_ipxact/tree/master` which contains a core-file with CAPI-version 1 and tried to migrate it to version 2 with following `fusesoc migrate-capi1-to-capi2 --inplace de0_nano_ipxact.core` which returned ``` usage:...
Hi @olofk, I have been successfully using fusesoc with Modelsim and cocotb for a while now. I wanted to update my core files to reflect the latest changes in edalize...
This PR adds a new provider for fetching data from a SVN server given the URL, an optional revision, and can ignore externals. The associated test simply fetches the .desktop...
When using the --no-export argument the generator cache gets placed in the `build//-/generator_cache `folder instead of the `.cache/fusesoc/generator_cache` folder. But this folder is removed at the start of each fusesoc...
Currently, the only option is to export either all files or none. This can be a problem if the files are several gigabytes in size or depend on other files...
I came across a use case today that I hadn't thought about before and is probably particular to our use case. We're using a Generator to convert Migen modules to...
Recently, I am dealing with [ibex-demo-system](https://github.com/lowRISC/ibex-demo-system). There are many cores and I find it hard searching for RTL in each .core file because they loop deeper in vendor directory. In...
logging.warn is an alias to logging.warning since Python 3.3 and will be removed in Python 3.13.
