Running xvlog and xelab

[hossein1387]

Previously, I had my own hdl wrapper :D but then I decided to use fusesoc since I believe it is much mature than what I have. In my build setup, this was what I was doing:

1. xvlog --sv [all my systemverilog files]
2. xvlog [all my verilog files]
3. xelab -debug typical -L secureip -L unisims_ver -L unimacro_ver testbench_top -L work.glbl -L blk_mem_gen_v8_4_3 --timescale 1ps/1ps

I was not able to find xvlog in fusesoc and when I tried to use it as a tool target, I got this warning:

WARNING: Unknown item xvlog in section Tools

What I have in my core file is like this:

CAPI=2:
name : ::pito:0
description: Barrel RISC-V core to control an array of Matrix Vector Units

filesets:
    rtl:
        files:
            - vsrc/rv32_instr.svh:
                is_include_file: true
            - vsrc/rv32_imm_gen.sv
            - vsrc/rv32_decoder.sv
            - vsrc/bram_32Kb.v
            - vsrc/rv32_data_memory.sv
            - vsrc/rv32_instruction_memory.sv
            - vsrc/rv32_alu.sv
            - vsrc/rv32_regfile.sv
            - vsrc/rv32_barrel_regfiles.sv
            - vsrc/rv32_core.sv
            - vsrc/rv32_next_pc.sv
            - vsrc/rv32_csr.sv
            - vsrc/rv32_barrel_csrfiles.sv
        file_type : systemVerilogSource
    tb:
        files:
            - verification/lib/rv32/rv32_defines.svh: 
                is_include_file: true
            - verification/lib/testbench/testbench_macros.svh:
                is_include_file: true
            - verification/lib/rv32/rv32_pkg.sv
            - verification/lib/pito/pito_pkg.sv
            - verification/lib/utils/utils.sv
            - verification/lib/rv32/rv32_utils.sv
            - verification/lib/pito/pito_inf.svh:
                is_include_file: true
            - verification/lib/pito/pito_monitor.sv
            - verification/lib/testbench/testbench_config.sv
            - verification/lib/testbench/testbench_base.sv
            - verification/tests/core/core_tester.sv
            - verification/lib/testbench/testbench_top.sv
        file_type : systemVerilogSource
targets:
    sim:
        default_tool: xsim 
        filesets:
            - tb
            - rtl
        toplevel: [rv32_core]
        description: Simulate the design
        tools: 
            xsim:
                xelab_options: [--debug,typical, -L, secureip, -L, unisims_ver, -L, unimacro_ver, -L, work.glbl, -L, blk_mem_gen_v8_4_3, --timescale, 1ps/1ps]
                xsim_options: []
        toplevel: testbench_top

then I ran this command:

fusesoc run --target=sim pito

In my previous build script, since I was building systemverilog files and verilog files before xelab most of the package import and includes was not necessary because they were already built into work directory. But with this core file, for most of my files, I had to add additional code to include files with is_include_file flag. I did this but now I am getting errors for some of the classes that I defined in verification/tests/core/core_tester.sv file and they are called by top module in verification/lib/testbench/testbench_top.sv which I do not get why it cannot find it? I can only think that I need to package my verification/tests/core/core_tester.sv and import it into my verification/lib/testbench/testbench_top.sv file. Is there something that I am missing?

Also, for backward compatibility, I much prefer to use the same code I had before using fusesoc (with no unnecessary includes). I believe this is not fusesoc issue but the way I call the tool through fusesoc.