Support VHDL/mixed language in VCS backend

[cmarqu]

Synopsys VCS-MX supports not only (System)Verilog as is the case with the backend right now but also VHDL, allowing mixed-language simulation. Some pointers:

• http://www.vlsiip.com/vcs/
• http://salinasv.blogspot.com/2011/05/simulating-mixed-language-hdl-using-vcs.html
• https://github.com/benreynwar/vunit/blob/vcsmx_interface/vunit/vcsmx_interface.py
• https://github.com/benreynwar/vunit/blob/vcsmx_interface/vunit/vcsmx_setup_file.py
• https://github.com/VUnit/vunit/issues/134

[olofk]

Thanks for reporting. The VCS backend should definitely support VHDL too. As I don't have access to VCS myself I would very much appreciate if some VHDL user with access to VCS could help out. Happy to review patches