Support for updating Vivado project files

[eine]

Since Vivado is a supported backend, I did expect some kind of project management features. For example, having some default IP-core assets that are updated. When top-level generics/parameters are updated in the EDAM file, these would be applied to the bd/bd.tcl, component.xml and xgui/*.tcl files. Is this supported at all? Or is the user expected to update generics in VHDL, in edalize and in the Vivado files too? In fusesoc/blinky/blob/master/nexys_a7/blinky.xdc IO constraints are defined, but I could not find any other Vivado-specific source.

From a wider perspective, I wonder how would edalize fit in a project for Zynq. Just a 'simple' design of a single accelerador with an AXI Stream input and an AXI Stream output. This would be an IP-core, instantiated in a project with the PS and a DMA. The point would be if edalize can update the files that correspond to the IP-core, rebuild it, and rebuild all the project.

[m-kru]

@eine I feel like there are quite a few, general questions in your comment. As I use Vivado backend quite extensively I am sure I am able to answer some of them. However, can you make a list with distinct questions:

1. ... ?
2. ... ?
3. ... ?

and make them a bit more verbose by providing use cases or describing what you would like to achieve?