Disabling yosys's synthesis

[Henkru]

The CXXRTL backend for Yosys allows the generation of C++ code that can simulate a digital design, similar to the Verilator. The write_cxxrtl command is not usually used in combination with the synthesized version of the design, but the edalize_yosys_template.tcl script always runs the synth_xxx command.

I propose adding the ability to disable the synth command through the tools_options. Currently, the arch field, which is used to generate the synth command, is required. I'm suggesting that when the arch is not set, then the synth command is omitted. This would not need the introduction of a new field nor change the ABI, as the current implementation causes Edalize to crash if arch is set to None.

I have drafted a PoC of the above. In addition, the PoC also introduces the yosys_write_options field, which allows for the passing of extra arguments to the write command, such as the optimization level for write_cxxrtl.

Before creating a pull request, I would like to hear your thoughts on this proposal.