Vivado block design support is broken

[shareefj]

This is really just tracking for myself since I implemented the change back in https://github.com/olofk/edalize/pull/290, but it looks like what I implemented is broken. I've just started using the flow on a second design and am hitting errors when Vivado tries to upgrade the BD. I'm using an UltraScale+ rather than a Zynq-7000 device in this project so not sure if that's the difference or the fact that I don't have any IPs outside of my BD this time.

Either way, the error I get looks like:

WARNING: [IP_Flow 19-4317] There are no IP instances in the project, so no report is generated.
WARNING: [Coretcl 2-176] No IPs found
ERROR: [Common 17-69] Command failed: No IP specified.  Please specify IP with 'objects'

where the error seems to be caused by line 60 of the project template.

Having looked again at the relevant section of the user guide, https://docs.xilinx.com/r/en-US/ug994-vivado-ip-subsystems/Upgrading-a-Block-Design-in-Non-Project-Mode, the correct command seems to be:

{% if bd_files -%}
{%- for bd in bd_files %}
report_ip_status
set bd [ open_bd_design {{ bd }} ]
current_bd_design $bd
upgrade_bd_cells [get_bd_cells -hier *]
close_bd_design $bd
set_property synth_checkpoint_mode None [get_files {{ bd }}]
generate_target all [get_files {{ bd }}]
{% endfor -%}
{%- endif %}

I'll open a PR for this but if anyone wants to take a look and double check then that would help.

Shareef.