corescore issues

Add VU19P target with 10K cores.

The board is proprietary so board support is just called vu19p. The synthesis, place & route requires at least 64GB of RAM and ~48H on classical machine (I7 7700K). Results...

enjoy-digital

HPCV2 K420T board updated from 1024 to 1276 cores! :)

HPCV2 K420T board updated from 1024 to 1276 cores! :) Changes to be committed: modified: corescore.core modified: rtl/hpc_k7_clock_gen.v

samsoniuk

Add cmod_a7_35 target.

3

This compiles fine with Vivado 2018.2, however when trying to connect with corecount, it does not print anything. Resource utilisation is as such: ``` +----------------------------+-------+-------+-----------+-------+ | Site Type | Used...

bl0x

Corescore on spartan6

4

I'm trying to add my board[ opos6ul_sp in the corescore project.](https://github.com/Martoni/corescore/commit/29af1313cc7e7f0842cfce885bacbe6f50cd98b0) but I'm stuck with a $clog2() problem. ``` ERROR:HDLCompiler:815 - "/…/workspace/build/corescore_0/src/serving_1.0.2/serving/serving.v" Line 42: System function call clog2 is not...

Martoni

Corescore/fusesoc doesn't check for correct edalize version install

1

I installed fusesoc in May 2020 to run corescore. Today, I ran it again, but it failed when compiling for the Trellis target. The particular error doesn't really matter, but...

tomverbeure

Can't launch corecount.py correctly

I managed to synthesize corescore for colorlight_5a75b. Seems to works but if I open terminal on uart I have an end of line problem : ```shell $ screen /dev/ttyUSB0 57600...

Martoni

Where are the dependencies?

1

Since this repository utilizes FuseSoC, how to find a submodule is less obvious compared to those using Makefile. For example, ` corescore/rtl/corescore_tinyfpga_bx.v` initializes the module `axis_async_fifo`, but searching the name...

nalzok