Olof Kindgren

The simple reason is that no one has written a testbench :) It should be pretty trivial though, and even if there isn't a verilator testbench available, you can still...

ok, I made a quick'n'dirty verilator testbench now starting from the one in mor1kx-generic. It needs some extra love, and doesn't stop unless you hit Ctrl-C, but at least I...

Ah. It might be that your version of Verilator is too old. The support for setting top-level parameters was added quite recently to verilator. If you're unable to use a...

Hmm... that's a good question, but unfortunately I can't give you a good answer. Maybe the best way to do it is to create a custom script that launches all...

ok, I got a little curious, so I decided to implement it myself as a python script. [This](https://gist.github.com/olofk/76b0b04181a7edd002a7529cf97ea325) launches all the OpenRISC tests, saves the contents of stdout and stderr...

Hi, Just wanted to let you know that I've seen the issue, but unfortunately I don't know enough about that core to give you an answer right away, and I...

The rationale here has been to replace the plusargs with parameters when I push new versions of a core, so that the current .core files are backwards compatible. I'm getting...

Unfortunately there is no testbench at all available for the Atlys system. I see that atlys.core claims to support simulations with Icarus Verilog, but that's not correct.

Should I drop the first patch that changes the RTL for now and just add verilator support to begin with?

I agree that a Python library would be very good to have. Since it's pretty much a 1 to 1 mapping with IP-XACT it would probably not be too much...