Øyvind Harboe

Statistics on simulation frequency dumped only for Treadle

4

There should be the same statistics printed for all simulators. - Startup time(here Treadle is expected to score much higher) - Simulation frequency - Total time ``` test ThingAMaBob Success:...

Java/Scala seems to cut the exception off before there's a line number of the step() printed, so I don't know which step() that timed out ``` [info] - should write...

Attached is [verilator_bug.zip](https://github.com/ucb-bar/chisel/files/798543/verilator_bug.zip), a tiny example that produces the error message below when you run "sbt run". There's not much that can be removed or changed before the problem disappears....

sphinxcontrib plantuml does not detect when a plantuml.jar falls back to png, leading to an exception

4

This is with sphinxcontrib-plantuml 0.20.1. Problem: plantuml.jar will silently fall back to .jar files. This can cause exceptions in sphinxcontrib-plantuml. ``` Encoding error: 'utf-8' codec can't decode byte 0x89 in...

No error message when using BoringUtils

1

I don't get these error messages from firtool displayed on the command line, only an exception dump when I run my design through chisel-circt: ``` circuit AptosNode : ^ :1:1:...

Error message drowns

1

The error message from firtool is drowned out. The line with the actual error message is an ```[info]``` line: ``` [info] Running CIRCT: 'firtool -format=fir -warn-on-unprocessed-annotations -verify-each=false --lowering-options=disallowPackedArrays --split-verilog --dedup...

Lock firtool version to chisel-circt version

1

That way chisel-circt versions would be idempotent: check out a given version of chisel-circt and you get an exact version of the firtool.... As it is today, I get errors...

Reduce the startup time for a Scala Unit-test by skipping Verilator compilation *and* design elaboration

1

To interface to an existing test-system, I would like to launch a test from the command line hundreds of times by passing different test-input vector files on the command line....

Improve RTLMP so that it can lay out mock-array in an array

2

### Description unzip [rtlmp.zip](https://github.com/The-OpenROAD-Project/OpenROAD/files/12808850/rtlmp.zip) ``` $ ./run-me-mock-array-asap7-base.sh OpenROAD v2.0-10574-gd04de2f32 [deleted] ``` Placement result, not an array:  ### Suggested Solution Should result in an array. ### Additional Context _No response_

Add feature to automate handling of clock insertion latency of Element in mock-array and mock-array itself

7

### Description The Element in the mock-array and mock-array itself has a clock insertion latency. The idea is that this clock insertion latency will keep increasing as one goes up...