Verilog-Projects 65 Bits Output

65 Bits Output

Open alfen-yu opened this issue 1 year ago • 0 comments

The SUM output port is declared as [64:0] instead of [63:0]. This will result in an extra bit in the output. If you want the output to be 64 bits, you should change the port declaration to output [63:0] SUM.

Jul 11 '23 07:07 alfen-yu

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65 Bits Output

Verilog-Projects
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