Nathaniel Wesley Filardo

OK, I tried and I'm sorry, but I don't think I'm going to be able to raise a PR in the near term. - `libusb1` requires the client to continue...

I confess I haven't been tracking this "reserved 1 [AG]CPERM bits" thread of conversation as closely as I perhaps should have been, sorry. I'll also preface this with "perhaps I've...

I've yet to see an example of software that can run with(out) a particular permission and retain its intended security properties. If you'll forgive a bit of an acknowledged hard-line...

To expand that a bit (@jrtc27 please complain if I've misunderstood): "It's reserved 1 so CBuildCap works in upwards-compatibility deployment scenarios, where hardware knows about (dependent) permissions that software does...

AFAICT, the CLIC `mcause` values will always be interrupts and so have the `Interrupt` bit (at index `XLEN-1`) set, and CHERI traps will always be synchronous exceptions and so have...

By `software error` do you mean `software check` (18)? I think we would prefer not to need `mtval2` in CHERIoT, because we certainly don't implement the hypervisor extension, so I...

I think that's right and agreeable to CHERIoT. :)

They stand a chance of working in the base ISA (ETA: or in Zcherihybrid), if there's memory near 0. This is specifically for instructions in cap mode.

@arichardson Yeah, I agree that in some sense "illegal instruction" is "better" than "CHERI tag violation" if the intent is to allow the instruction to be repurposed (and yes, indeed),...

Just to make sure it isn't missed... In addition to the clever trick David's pointing out, this marking as extensible is intended to apply to more than just high-alignment-requiring LC/SC...