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ENH: Add CPU feature detection for SVE2
Proposed new feature or change:
Add CPU feature detection for SVE2. On wide CPU cores the Scalable Vector Extension has the potential to increase performance manyfold compared to NEON.
SVE2 is supported on most Armv9 cores, including the Arm Cortex-A510, Cortex-A710, Cortex-X2 and Neoverse N2 CPU designs. This means it's (to be) found in a huge amount of devices.
Arm documentation: https://developer.arm.com/Architectures/SVE
Introducing SVE2
This section introduces the Scalable Vector Extension version two (SVE2) of the Arm AArch64 architecture.
Following the development of the Neon architecture extension, which has a fixed 128-bit vector length for the instruction set, Arm designed the Scalable Vector Extension (SVE). SVE is a new Single Instruction Multiple Data (SIMD) instruction set that is used as an extension to AArch64, to allow for flexible vector length implementations. SVE improves the suitability of the architecture for High Performance Computing (HPC) applications, which require very large quantities of data processing.
SVE2 is a superset of SVE and Neon. SVE2 allows for more function domains in data-level parallelism. SVE2 inherits the concept, vector registers, and operation principles of SVE. SVE and SVE2 define 32 scalable vector registers. Silicon partners can choose a suitable vector length design implementation for hardware that varies between 128 bits and 2048 bits, at 128-bit increments. The advantage of SVE and SVE2 is that only one vector instruction set uses the scalable variables.
This enhancement might be similar to https://github.com/numpy/numpy/pull/20821 and https://github.com/numpy/numpy/pull/20552.
Some other projects that have implemented SVE2 support, which might or might not be useful resources:
- Linux ARM Kernel: arm64: Expose SVE2 features for userspace
- https://github.com/halide/Halide/pull/6781
- https://github.com/openjdk/jdk/pull/8258
Arm’s client CPU cores targeted for 2023 devices have been announced, the Cortex-X3, Cortex-A715 and refreshed Cortex-A510, and all boast faster SVE2 implementations (especially at the decoding stage). The maximum CPU cluster size has been expanded from 8 to 12 cores, making it more likely these cores will also end up in laptops.
Hi, @EwoutH I am trying an implementation for SVE. Here is the source code, and I have confirmed that it works on Fujitsu A64FX (Armv8.2a + SVE 512 bits).
I am planning to submit a pull request in the near future. Are you working on an SVE/SVE2 implementation?
Awesome, thanks a lot! This is also great timing with the announcement of Neoverse V2 and E2 CPU cores!
Do you by any chance have any performance benchmarks? (see maybe benchmark docs)