fixing errata 12 on master branch

[samiralavi]

[sakugava]

while (((eir = readReg(EIR)). Is it correct?

[samiralavi]

Yes it is, (((eir = readReg(EIR)) & (EIR_TXIF | EIR_TXERIF)) == 0) we have 3 separate conditions, first : (eir = readReg(EIR)) it puts the read result into eir and then eir is returned second : (EIR_TXIF | EIR_TXERIF) third : And of these two conditions (((eir = readReg(EIR)) & (EIR_TXIF | EIR_TXERIF)) == 0) Also we can change it to be more clear : (((eir = readReg(EIR)) & (EIR_TXIF | EIR_TXERIF)) == false) or (!((eir = readReg(EIR)) & (EIR_TXIF | EIR_TXERIF)))

[samiralavi]

I once had a problem that when I would connect a ENC28j60 board to raspberry pi directly, after some time the IC would be stuck. After a lot of search, I finally made it work, by adding this fix to master branch.

[Benjamin-Langlois]

while (((eir = readReg(EIR)) & (EIR_TXIF | EIR_TXERIF)) == 0)

always results in 0 because:

(EIR_TXIF | EIR_TXERIF) == (2 | 8) == 10

and (X & 10) == 0

Shouldn't it be && instead of &?