VHDL-2019 vs Your Extensions

[JimLewis]

In your documentation, please be sure to note what is a VHDL-2019 directive vs. what are your extensions.

In particular, please be sure to note that `define and `include are your extensions.

If you think your extensions should be part of the standard, then participate.
We also use git for our issues. See: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues

Furthermore, if you are capable of writing a tool like this and you use git, you would be a valuable asset to the team - yes we recruit people from the open source community :)