nmigen-issue-migration

**Comment by [HarryHo90sHK](https://github.com/HarryHo90sHK)** _Tuesday Sep 24, 2019 at 04:36 GMT_ ---- @whitequark > 9. **Debatable:** I propose to unify CSRStatus and CSRStorage, and instead use per-bit writability. This is partly...

**Comment by [whitequark](https://github.com/whitequark)** _Tuesday Sep 24, 2019 at 12:02 GMT_ ---- > Would you guys think it's better to call all the read/write data and strobe signals from the CPU...

**Comment by [xobs](https://github.com/xobs)** _Wednesday Sep 25, 2019 at 08:05 GMT_ ---- I've been working on `lxsocdoc` which can be inserted into a flow after verilog generation. An example of the...

**Comment by [programmerjake](https://github.com/programmerjake)** _Thursday Aug 22, 2019 at 23:58 GMT_ ---- I would think that most SRAMs don't get reset on ASICs either, so that shouldn't interfere with BRAM inference.

**Comment by [whitequark](https://github.com/whitequark)** _Friday Aug 23, 2019 at 00:01 GMT_ ---- > I would think that most SRAMs don't get reset on ASICs either, so that shouldn't interfere with BRAM...

**Comment by [programmerjake](https://github.com/programmerjake)** _Friday Aug 23, 2019 at 00:19 GMT_ ---- Ah, missed that.

**Comment by [RobertBaruch](https://github.com/RobertBaruch)** _Saturday Oct 12, 2019 at 14:38 GMT_ ---- (will be updating the docs about signedness with the new `signed` constructor)

**Comment by [whitequark](https://github.com/whitequark)** _Saturday Oct 12, 2019 at 19:55 GMT_ ---- Looking at how things go, I will get around to docs somewhere around November-December. A number of other people...

**Comment by [whitequark](https://github.com/whitequark)** _Friday Dec 21, 2018 at 06:57 GMT_ ---- # Lattice iCE40 ## DRAM No distributed RAM. ## BRAM Configurable as 2048x2, 1024x4, 512x8 or 256x16. Block RAM...

**Comment by [nakengelhardt](https://github.com/nakengelhardt)** _Friday Dec 21, 2018 at 08:22 GMT_ ---- # Xilinx (7 Series and UltraScale) ## DRAM - supports asynchronous read - if synchronous read is used, write...