Nirvedh Meshram

I dont think the compiler can support such a dispatch region, I think it would be more interesting to see how we ended up forming this region due to https://github.com/iree-org/iree/pull/18618...

I am able to vectorize this with this patch https://github.com/llvm/llvm-project/compare/main...nirvedhmeshram:llvm-project:conv_i1 I will try to land it upstream.

I have a PR open upstream for this https://github.com/llvm/llvm-project/pull/109480

This was fixed by the upstream PR

This failure is in the lowering of a (i8,i8)->i32 batch matmul op here is a smaller repro IR ``` module { func.func @punet_repro(%11 : tensor, %12 : tensor, %13 :...

I have a WIP PR https://github.com/iree-org/iree/pull/18433 that solves seems to solve the issue (at least the batchmatmul compiles), I will clean it up and add some e2e tests to it...

@pdhirajkumarprasad For this and all the other bugs you filed recently, could you please add this flag to `--mlir-print-ir-after-all` to the iree-compile command and copy the dump to a file...

> Here is the llvm IR for the above example: https://gist.github.com/qedawkins/acce2625d09bac6caa51f53a304df9fe > > Disabling the LoadStoreVectorizerPass appears to fix the issue: https://github.com/llvm/llvm-project/blob/6fcea431eed78f75e8ddb48e074c0078b93c109f/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp#L1230 @qedawkins can you share the .rocmasm files generated...

@Groverkss this is not urgent, so whenever you have cycles could you please take a look.

> Can we observe the difference using the gemm shapes in https://github.com/nod-ai/iree-kernel-benchmark ? As I am running it I am realizing that all of but three shapes in the benchmark...