nickg
Caught signal 11 (SEGV_MAPERR) [address=(nil), ip=0x55d355824159]
I am getting this error when using VHDL-2019
*** Caught signal 11 (SEGV_MAPERR) [address=(nil), ip=0x55d355824159] ***
[0x55d3557755ed] [0x7fe644cfe32f] (/usr/lib/x86_64-linux-gnu/libc.so.6) [0x55d355824159] [0x55d3557d06a6] [0x55d3557d186f] [0x55d3557d799c] [0x55d3557d1885] [0x55d35577222c] [0x55d35576df88] [0x55d355769aa5] [0x7fe644ce31c9] (/usr/lib/x86_64-linux-gnu/libc.so.6) [0x7fe644ce328a] (/usr/lib/x86_64-linux-gnu/libc.so.6) __libc_start_main [0x55d35576b124]
nvc 1.16.1 (e230787) (Using LLVM 18.1.3) [x86_64-pc-linux-gnu]
Please report this bug at https://github.com/nickg/nvc/issues
I think the issue is related to refrencing whole view of nested views. I need to do this because cocotb does bind to VHDL-2019 interfaces.
-- instantiation of axiLite_reg_inst
axiLite_reg_inst : entity work.axiLite_reg(rtl)
generic map (
g_NUM_W_REG => 4,
g_W_REG_INIT => s_readRegister, -- Initial values for write registers
g_NUM_R_REG => 4
)
port map (
i_axil_clk => s_axil_aclk,
i_axil_reset => s_axil_areset,
--
axil_agent.writeTxn.wrAddrCh.awaddr => s_axil_awaddr,
axil_agent.writeTxn.wrAddrCh.awvalid => s_axil_awvalid,
axil_agent.writeTxn.wrAddrCh.awready => s_axil_awready,
--
axil_agent.writeTxn.wrDataCh.wdata => s_axil_wdata,
axil_agent.writeTxn.wrDataCh.wstrb => s_axil_wstrb,
axil_agent.writeTxn.wrDataCh.wvalid => s_axil_wvalid,
axil_agent.writeTxn.wrDataCh.wready => s_axil_wready,
--
axil_agent.writeTxn.wrRespCh.bresp => s_axil_bresp,
axil_agent.writeTxn.wrRespCh.bvalid => s_axil_bvalid,
axil_agent.writeTxn.wrRespCh.bready => s_axil_bready,
--
axil_agent.readTxn.rdAddrCh.araddr => s_axil_araddr,
axil_agent.readTxn.rdAddrCh.arvalid => s_axil_arvalid,
axil_agent.readTxn.rdAddrCh.arready => s_axil_arready,
--
axil_agent.readTxn.rdDataCh.rdata => s_axil_rdata,
axil_agent.readTxn.rdDataCh.rresp => s_axil_rresp,
axil_agent.readTxn.rdDataCh.rvalid => s_axil_rvalid,
axil_agent.readTxn.rdDataCh.rready => s_axil_rready,
--
writeRegister => s_writeRegister,
readRegister(1 downto 0) => s_readRegister(1 downto 0), -- Only the first two registers are used
readRegister(3 downto 2) => s_writeRegister(3 downto 2)
); -- end of axiLite_reg_inst
I came up with a reproducer for this:
entity issue1208 is
end entity;
architecture test of issue1208 is
type bus_t is record
valid : bit;
ack : bit;
end record;
view bus_master of bus_t is
valid : out;
ack : in;
end view;
alias bus_slave is bus_master'converse;
type doublebus_t is record
slave, master : bus_t;
end record;
view double_master of doublebus_t is
slave : view bus_slave;
master : view bus_master;
end view;
signal bs, bm : bus_t;
begin
b : block is
port (double : view double_master);
port map (
double.slave => bs,
double.master => bm
);
begin
end block;
end architecture;
nvc --std=2019 -a issue1208.vhd
nvc --std=2019 -e issue1208
** Fatal: (init): tree kind T_REF does not have item I_VALUE
> ../test/parse/issue1208.vhd:29
|
29 | port (double : view double_master);
| ^^^^^^^^^^^^^
[0x564345b60830] ../src/object.c:261 object_lookup_failed
diag_emit(d);
--> show_stacktrace();
fatal_exit(EXIT_FAILURE);
[0x564345b15388] ../src/tree.c:847 tree_value
{
--> item_t *item = lookup_item(&tree_object, t, I_VALUE);
assert(item->object != NULL);
[0x564345b8c3d5] ../src/lower.c:11725 lower_port_map
--> view = tree_value(view);
}
[0x564345b8dd1f] ../src/lower.c:12171 lower_ports
if (!hset_contains(direct, map))
--> lower_port_map(lu, block, map, map_regs[i]);
else if (poison != NULL && tree_subkind(map) == P_NAMED) {
[0x564345b8ff35] ../src/lower.c:12835 lower_instance
lower_generics(lu, block, primary);
--> lower_ports(lu, ds, block);
lower_decls(lu, block);
[0x564345b3e507] ../src/elab.c:1345 elab_lower
{
--> ctx->lowered = lower_instance(ctx->registry, ctx->parent->lowered, shape,
elab_driver_set(ctx), ctx->cover, b);
[0x564345b411af] ../src/elab.c:2085 elab_block
if (error_count() == base_errors) {
--> elab_lower(b, NULL, &new_ctx);
elab_stmts(t, &new_ctx);
[0x564345b40eb4] ../src/elab.c:2030 elab_stmts
case T_BLOCK:
--> elab_block(s, ctx);
break;
[0x564345b3ecda] ../src/elab.c:1465 elab_architecture
elab_stmts(entity, &new_ctx);
--> elab_stmts(arch_copy, &new_ctx);
}
[0x564345b41847] ../src/elab.c:2211 elab_vhdl_root_cb
if (error_count() == 0)
--> elab_architecture(bind, arch, config, ctx);
}
[0x564345c56791] ../src/rt/model.c:3795 call_with_model
MODEL_ENTRY(m);
--> (*cb)(arg);
}
[0x564345b41b62] ../src/elab.c:2266 elab
if (vhdl != NULL)
--> call_with_model(m, elab_vhdl_root_cb, &ctx);
else
[0x564345ac4de5] ../src/nvc.c:553 elaborate
--> tree_t top = elab(obj, state->jit, state->registry, state->mir, cover,
NULL, state->model);
[0x564345ac94c4] ../src/nvc.c:2459 process_command
case 'e':
--> return elaborate(argc, argv, state);
case 'r':
[0x564345ac9a6a] ../src/nvc.c:2625 main
--> const int ret = process_command(argc, argv, &state);
nvc --version
nvc 1.17-devel (1.15.0.r221.g5ea57533) (Using LLVM 14.0.0) [debug]
Copyright (C) 2011-2025 Nick Gasson
This program comes with ABSOLUTELY NO WARRANTY. This is free software, and
you are welcome to redistribute it under certain conditions. See the GNU
General Public Licence for details.
Thanks @NikLeberg! I've fixed that crash although I'm not sure if it's the same as @Ahmad-Zaklouta hit as the "tree kind T_REF does not have item I_VALUE" message should appear in non-debug builds too. Would be good to test again with the latest master though.
I need to do this because cocotb does bind to VHDL-2019 interfaces.
VHPI hasn't been extended to cover views and other VHDL-2019 features. I'm not sure what happens at the moment if you have view mode for a top level port. What error do you get from cocotb? We could perhaps fake it so those ports appear as vhpiInoutMode.
@nickg I have a VHDL top-level file that have normal in/out ports. this file instantiate an entity that have nested view as port.
This is the result from the latest master without cocotb. not sure how to print detailed msg like above:
*** Caught signal 11 (SEGV_MAPERR) [address=(nil), ip=0x559a67449354] ***
[0x559a673a26d5] ../src/util.c:906 signal_handler.lto_priv.0 [0x7fefc0e4132f] (/usr/lib/x86_64-linux-gnu/libc.so.6) [0x559a67449354] ../src/tree.c:627 lower_port_map.lto_priv.0 [0x559a673fba8e] ../src/lower.c:12074 lower_instance [0x559a673fba8e] ../src/lower.c:1345 elab_lower.lto_priv.0 [0x559a673fcabc] ../src/elab.c:1463 elab_architecture.lto_priv.0 [0x559a674025bb] ../src/elab.c:1643 elab_stmts.lto_priv.0 [0x559a673fcad2] ../src/elab.c:1465 elab_architecture.lto_priv.0 [0x559a6739d1a9] ../src/elab.c:2211 elab [0x559a6739d1a9] ../src/elab.c:553 elaborate [0x559a67399709] ../src/nvc.c:2459 process_command [0x559a67395d5a] ../src/nvc.c:2625 main
nvc 1.17-devel (1.16.0.r49.ga464013d) (Using LLVM 18.1.3) [x86_64-pc-linux-gnu]
Please report this bug at https://github.com/nickg/nvc/issues
Can you try enabling debug mode with configure --enable-debug and see if that triggers any assertion failures?
Hey! This is the result from the latest master with --enable-debug
I tried to compile it with Riviera Pro and it pass the compilation.
nvc: ../src/lower.c:11617: lower_port_map: Assertion `elem != NULL' failed.
*** Caught signal 6 (SIGABRT) ***
[0x564ed8ef68d9] ../src/util.c:906 signal_handler [0x7fef0e3d332f] (/usr/lib/x86_64-linux-gnu/libc.so.6) [0x7fef0e42cb2c] (/usr/lib/x86_64-linux-gnu/libc.so.6) pthread_kill [0x7fef0e3d327d] (/usr/lib/x86_64-linux-gnu/libc.so.6) raise [0x7fef0e3b68fe] (/usr/lib/x86_64-linux-gnu/libc.so.6) abort [0x7fef0e3b681a] (/usr/lib/x86_64-linux-gnu/libc.so.6) [0x7fef0e3c9516] (/usr/lib/x86_64-linux-gnu/libc.so.6) __assert_fail [0x564ed8f88212] ../src/lower.c:11617 lower_port_map [0x564ed8f8e7f0] ../src/lower.c:12074 lower_ports [0x564ed8f8e7f0] ../src/lower.c:12734 lower_instance [0x564ed8f4f324] ../src/elab.c:1345 elab_lower [0x564ed8f517dc] ../src/elab.c:1463 elab_architecture [0x564ed8f51983] ../src/elab.c:1643 elab_stmts [0x564ed8f517f4] ../src/elab.c:1465 elab_architecture [0x564ed90244b0] ../src/rt/model.c:3795 call_with_model [0x564ed8f546bc] ../src/elab.c:2266 elab [0x564ed8eefa4e] ../src/nvc.c:553 elaborate [0x564ed8eefa4e] ../src/nvc.c:2411 process_command [0x564ed8eec99b] ../src/nvc.c:2575 main
I haven't found a way to reproduce this yet. I put some extra debug which should cause it to exit with a fatal error and print the location/type involved. Can you try again with the latest master branch? If possible try to narrow it down to a minimal reproducer.
now I am getting this error with the latest master. it seems it is not beign able to handle nested views
** Fatal: (init): missing element mode indication for field ARADDR type AXILITE_RDADDRCH_T view AXILITE_AGENT_V > /issue1208.vhdl:92 | 92 | axil_agent.rdAddrCh.araddr => s_axil_araddr,
this is a reproducer
--------------------------------------------------------------------------------`
-- PACKAGE DECLARATION
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package axiLite_pkg is
-- AxiLite Read Address channel
type axiLite_rdAddrCh_t is record
-- Handshake signals
arvalid : std_logic;
arready : std_logic;
-- Payload signals
araddr : std_logic_vector(7 downto 0);
end record axiLite_rdAddrCh_t;
view axiLite_rdAddrCh_Host_v of axiLite_rdAddrCh_t is
-- Handshake signals
arvalid : out;
arready : in;
-- Payload signals
araddr : out;
end view axiLite_rdAddrCh_Host_v;
alias axiLite_rdAddrCh_Agent_v is axiLite_rdAddrCh_Host_v'converse;
------------------------------------------------------------------------------
-- AxiLite Read
type axiLite_t is record
rdAddrCh : axiLite_rdAddrCh_t;
end record axiLite_t;
view axiLite_Host_v of axiLite_t is
rdAddrCh : view axiLite_rdAddrCh_Host_v;
end view axiLite_Host_v;
alias axiLite_Agent_v is axiLite_Host_v'converse;
------------------------------------------------------------------------------
------------------------------------------------------------------------------
end package axiLite_pkg;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.axiLite_pkg.all;
entity axiLite_reg is
port (
i_axil_clk : in std_logic; -- Main clock
i_axil_reset : in std_logic; -- reset, active high
-- AXI4-Lite interface
axil_agent : view axiLite_Agent_v of axiLite_t
);
end entity axiLite_reg;
architecture rtl of axiLite_reg is
signal s_axil_agent_if : axiLite_t;
begin
-- out
axil_agent.rdAddrCh.arready <= s_axil_agent_if.rdAddrCh.arready;
-- in
s_axil_agent_if.rdAddrCh.arvalid <= axil_agent.rdAddrCh.arvalid;
s_axil_agent_if.rdAddrCh.araddr <= axil_agent.rdAddrCh.araddr;
end architecture rtl;
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
--------------------------------------------------------------------------------
entity issue1208 is
port (
-- AXI4Lite
s_axil_aclk : in std_logic;
s_axil_areset : in std_logic;
--
s_axil_arvalid : in std_logic;
s_axil_arready : out std_logic;
s_axil_araddr : in std_logic_vector(7 downto 0);
);
end entity issue1208;
architecture str of issue1208 is
begin -- start of architecture --
axiLite_reg_inst : entity work.axiLite_reg(rtl)
port map (
i_axil_clk => s_axil_aclk,
i_axil_reset => s_axil_areset,
--
axil_agent.rdAddrCh.araddr => s_axil_araddr,
axil_agent.rdAddrCh.arvalid => s_axil_arvalid,
axil_agent.rdAddrCh.arready => s_axil_arready
); -- end of axiLite_reg_inst
end architecture str;
--------------------------------------------------------------------------------