Daniel "Thready" Nitecki comments

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                                            Daniel "Thready" Nitecki

`include directive should be allowed anywhere

~~~Verilog always @( * ) begin if ( cond1 ) begin case ( sig_key ) `DEF_CASE1 : sig_name

`include directive should be allowed anywhere

When instantiating module and using some ~~~ ... .port_name ( `DEF_VAL ), ... ~~~ for constant port value - I also get "no viable alternative at input" for ` sign