nelsobe

That is exactly what we noticed - always the top half of INIT_3F was all 0's.

@acomodi Thanks for the reply. This is helpful. When you talk about random mapping of IOs, are you saying there is a way to ask the tools to map them...

@mkurc-ant I have attached the synth_log as well as the original .sv file (part of a bigger project). It looks like yosys is not inferring a bram for the inst_memory....

@mkurc-ant @tmichalak Thanks for the follow ups we are seeing on some of these issues. We are slowly debugging and doing workarounds and now have a handful of our student...

@mkurc-ant @tmichalak @mithro Any news on item 4 in the comment above? We would like to test the latest Surelog plugin with f4pga-examples and are waiting for it to be...

@mkurc-ant @tmichalak Have confirmed the error has to do with the reset clause, NOT the conditional read clause. Assume, but don't know for sure, that this is a synthesis problem...

@mkurc-ant @tmichalak Any word on this one? As mentioned above, I have confirmed the error has to do with the reset clause in the code.

@mkurc-ant Any word on whether the instructions are now up to date so the latest fixes are inckluded?

I believe I get this error when I have had a missing signal in my .xdc file...

@mithro @acomodi @tmichalak @mkurc-ant Would be interested in any feedback you can provide.