Computer-Architecture
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nblintao
nblintao
A pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and cache.
Computer-Architecture
This is the laboratory assignment for the course Computer Architecture.
The final result of this project is a pipelined MIPS CPU supporting 31 MIPS instructions, interrupt and the cache.
My collaborator is Yuheng ZHOU.
nblintao