Ned Bingham

Feature Request channel-source-none

1

This source wouldn't actually source any tokens, it would just keep the data rails neutral.

channel-source-args doesn't completely reset previous channel-rsource effect

1

``` deftype _c1of2 R.f+ ~_R.t -> R.t+ Reset | R.f | R.t -> L.e- ~R.e & ~L.f -> _R.f+ ~R.e & ~L.t -> _R.t+ _R.f -> R.f- _R.t -> R.t-...

haccreate assertion failure -- template typedef parameter binding

1

``` template defproc x() { } template typedef x x2; x2 a; ``` ``` haccreate test.prso test.prso-c Error unroll-resolving parameter values. ERROR in expression 1 of param expr list: pint-val-ref...

haco assertion failure -- template typedef parameter transformation

5

``` export template defchan eMx1ofN

Segmentation fault -- memory allocation?

2

``` #FILE "x.hac" %{ pint TOOL_SIM = 1; pint TOOL_NETLIST = 2; %} #FILE "y.prs" %{ #FILE "z.prs" %{ #FILE "w.prs" %{ preal pn = 2.0; pint lsz = 10;...

We need to generate the verilog and spice testbenches for prsim-verilog-spice cosimulation for Synopsys VCS and Cadence Incisive. For example, if we have the following files: test.prs: ``` import "source.prs";...

hacprsim false positive error on channel connections

1

export defchan ev1of2 _ch_e- _ch_e => ch.f- _ch_e | ~_ch_e -> ch.t- } ch.v = ch.f; } source dut; prsim> channel dut.ch ev:0 :0 d:2 Channel acknowledge is not allowed...

when running spice-verilog-prsim cosimulation, all variations of $prsim_cmd("timing random") will hang.

It looks like you forgot to implement watchall-values

feature request for compile time assert to print message

1

spec { assert() } needs to be able to print a given message. Maybe like this? spec { assert() }