The bug caused by the order of `lower` and `ssa`

[weiwenhao]

Following the SSA phase, the temp_var generated in the lower phase was not constructed during the live-in phase of SSA. This resulted in missing virtual register replacements during register allocation.

In fact, the linear scan register paper proposed a coarse-grained live estimation scheme. It was previously discovered that this caused virtual register replacement exceptions due to live omissions. The solution at the time was to replace the coarse-grained live estimation with the precise live estimation from SSA. Now, the real issue might be the omission of lower temporary variables.