CI All Things!

[LeStarch]

F´ Version
Affected Component

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Feature Description

More improvements that can be made to CI!

• [ ] Various FW_CONFIG options
• [ ] Baremetal support
• [x] RPI CI reboot on failure: the RPI CI setup often fails for reasons unknown that a reboot of the pi fixes. It could auto reboot on failure and require less hand-holding.
• [ ] Configuration flags (FpConfig.hpp) ...more will be added

[SterlingPeet]

reminder to myself that I need to gather up some hardware

[ThibFrgsGmz]

Maybe it would be interesting to put in the CI the construction of a reference binary from several buildchain.

From what I could see, this is a good practice for software trying to support different architectures, like ThreadX which has in its CI the build with Cortex-M0/3/4/7.

If we follow this logic, it could be interesting to add in the CI the build of the reference binary with the following buildchain (for example):

• ARM R5 g++ compiler/linker (cortex-R5 baremetal): armr5-none-eabi-g++
• ARM v8 Linux g++ compiler/linker (cortex-A53 linux): aarch64-linux-gnu-g++
• ARM v8 g++ compiler/linker (cortex-A9 baremetal) : arm-none-eabi-g++
• GNU RISC-V Cross C++ compiler/binder (baremetal): riscv64-unknown-elf-g++
• GNU ARM Cross C++ compiler/associator (cortex-M3 baremetal): arm-none-eabi-g++.

Cortex-A53 and Cortex-R5 are integrated on the Zynq UltraScale+MPSoC platforms from Xilinx.

RISC-V is used on the Polarfire SoC from Microchip.

Then, for the execution of the unit tests associated with these cross-compiled binaries, they can be performed on emulators like QEMU or Renode.

[LeStarch]

That is the dream, but first we need solid toolchain implementations for these platforms...

[LeStarch]

#1443 has another CI improvement.