Megan Wachs
Megan Wachs
Would you say this serves more as an example application of Chisel than a UART IP we are encouraging people to use in their designs and tape outs? I think...
> My main use-case in the past has been that I wanted to see the signal on a VCD trace. This does not require us to forgo any optimizations, only...
The use case is a module which is parameterized, what is the type of its fields that might depend on the paramterization. One alternative might be (if we supported Either...
I guess you don't need an Either for this, you can just do it with Type parameters and a `gen`.
Discussed this again with @jackkoenig . The main limitation of this PR as it is is that we lose the "what is the prefix (ad-hoc namespace)" and "what is the...
Since we're still working on this, I am going to move this to DRAFT until we've done some of the experiments. This is a great first step, I think the...
You don’t need verilator to generate the verilog or the documentation. The command “sbt docs/mdoc” should work without it
Hi @Shorla , were you able to connect with @Burnleydev1 / get the docs build command to work? I think the next step is to add the test cases: a)...
> I am to add test cases to my scastie, My result should be directly added to the document or first be discussed here? I think ultimately it would be...
> a) When all I did was flip the direction of each of the arrows, the Verilog remained the same, with no errors. Great, let's add that. Perhaps for each...