Michael Singer comments

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                                            Michael Singer

CLKIN_A can't actually be a clock

I found another possibility what `CLKIN_A` could be used for: It is directly connected to the CPU core, so my guess is that the CPU can drive this wire low...

CLKIN_A can't actually be a clock

Ok, I'm very certain now that it is driven by the CPU. I just tested it. The STOP instruction causes the `XO` pin to stop clocking. This is even the...

LYXE wrongly connected to LORU

Just realized `LYXE` is actually a RS latch. See #29. This means, the `S` input of latch `LYXE` is driven by `LAVY`, the `R` input of `LYXE` is driven by...

Clock inputs of FF25 register need to be inverted one more time

Same goes for register FF10 (NR10) on page 11.

Clock inputs of FF25 register need to be inverted one more time

And FF17 (NR22) on page 14. Only the upper five flip-flops are missing an inverter at their clock inputs. You already gave that inverter a name in Inkscape (`ELAS`), but...

CH3_REGS and CHANNEL3 errors (schematic side)

I already found the solution to your second error. Please see #42. Also important to fix the length counter is #40. I disagree with the first "error" though. It actually...

Cells labelled "BUFFER?" could be just simple connections to the supply rails

I was checking my suspicion that those bigger tri-state drivers like ``TAHY`` may be weak drivers. I think this wouldn't work either, because then ``TAHY`` ... ``SEDU`` would weakly drive...

There must be two types of tri-state driver cells; ones with high active and ones with low active enable inputs

Ok, I think I just went through all of them, so I just add them here. It looks like most of the tri states have an active low enable input....

There must be two types of tri-state driver cells; ones with high active and ones with low active enable inputs

In the top right corner of page 8, the tri-state cells ``ANAR`` ... ``KEJO`` and ``LYNA`` ... ``AJOV`` must be active low, too. In normal operation, when ``!(T1)T2`` is not...

All input buffers are inverting

You can also check `D0_IN`-`D7_IN` on page 8. They get latched and the `Q` output of the latches goes through the smaller tri-states, which invert the signal. So the input...