vscode-verilog-hdl-support
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mshr-h
Variables cannot be completed automatically
Describe the bug Variables cannot be completed automatically
Environment:
- VS Code version: 1.63.2 (user setup)
- Extension version v1.5.3
- OS: Windows_NT x64 10.0.22000
Screenshot at failure
But if I don't save the file as .v, it can work normally
I met the same bug, and I changed the VSCode version back to 1.61, then the autocomplete works rightly.
I met the same bug, and I changed the VSCode version back to 1.61, then the autocomplete works rightly.
I now directly replace it with other plug-ins, such as TerosHDL or FPGA Develop Support.
I was able to fix this by setting word completion to current document instead of all documents.
Thsi seems to be a change in behavior in VS code.
The mentioned other extensions are not really usable, especially Teros HDL tries to impose its complete workflow onto you.
@markusdd I've just found that setting, but after saved as .v file the 'abc' intellisense still disappear permanently. So we can't autocomlete variables and other keywords like 'input' 'output' 'assign' ?
@markusdd ok, but it's really confusing why some key words are still not supported as snippets...... is there any other verilog editors recommended on Win10?
