vscode-verilog-hdl-support
vscode-verilog-hdl-support copied to clipboard
[BUG] Unable to parse (some) ModelSim lint messages
Describe the bug When I was trying to use modelsim to lint a file, the extension gave wrong parse result:
Environment:
- OS: Windows_NT x64 10.0.19043
- VS Code version: 1.61.2 (system setup)
- Extension version: v1.5.0
- lint: ModelSim Starter Edition 2020.1
Steps to reproduce Use ModelSim to lint the code below:
`timescale 1 ns /1 ns
`define AandBH 10'b0100000000
`define AorBH 10'b0010000000
module ArithmeticUnit (
A, B,
B15to0, AandB, AorB, notB, shlB, shrB, AaddB, AsubB, AmulB, AcmpB,
aluout, cin, cout, zout);
input [15:0] A, B;
input B15to0, AandB, AorB, notB, shlB, shrB, AaddB, AsubB, AmulB, AcmpB;
input cin;
output [15:0] aluout;
output cout,zout;
reg [15:0] aluout;
reg cout,zout;
always @(
A or B or B15to0 or AandB or AorB or notB or shlB or shrB or AaddB or AsubB or AmulB or AcmpB or cin
)
begin
cout = 0; aluout = 0;zout=0;
case ({B15to0, AandB, AorB, notB, shlB, shrB, AaddB, AsubB, AmulB, AcmpB})
`AorBH: //add your code
`AandBH: //add your code
default: aluout = 0;
endcase
if (aluout == 0) zout = 1'b1;
end
endmodule
Log
[Info] modelsim lint requested
[Info] 4 errors/warnings returned
Expected behavior L25 and L26 should be underlined according to messages from ModelSim.
Actual behavior

Additional context Other files' lint result can be parsed well. I have tried to move this file to another directory but the problem remained.