vscode-verilog-hdl-support
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mshr-h
[BUG] the highlighter does not disable or highlight the codes with `ifdef
Hi,
for example since we have not defined master ,it should make it gray or disabled color for this code inside the ifdef Master endif part. But for now adding or removing these `ifdef line of code does nothing!
ifdef Master LanTxFIFO myLanTxFIFO ( .rst(Vio[0]), // input rst .wr_clk(w_CLK96MHz), // input wr_clk .rd_clk(w_CLK96MHz), // input rd_clk .din(wFIFODin), // input [15 : 0] din .wr_en(wFIFOWe), // input wr_en .rd_en(wTX_EN), // input rd_en .dout(wLanTxData), // output [15 : 0] dout .full(wFull), // output full .empty(wEmpty), // output empty .prog_full(wProgFull), // output prog_full .prog_empty(wProgEmpty) // output prog_empty ); endif
I am having the same issue. This package doesn't highlight `ifdef keyword.
