Module last parameter syntax highlight error

[sheep94lion]

The last parameter of a module in Verilog is shown in incorrect color:

[alexisfrjp]

You should provide the file to reproduce the error. I've never seen this error.

[fishcrap]

I do encounter the same problem. If keyword wire is omitted in the last line of a module definition, the parameter will be in wrong color.

[DLehenbauer]

@alexisfrjp - The key to reproducing this bug is to put the closing ')' on the next line.

As you can see, this causes the last variable to be incorrectly highlighted as a keyword:

If you move the closing ')' to the same line as the last variable the highlighting is correct:

To reproduce, simply create an 'empty.v' file and paste the following:

module repro(
    input white,
    input blue
);
endmodule;