vscode-systemverilog-support
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Instantiate module command does not support interfaces
While using instantiate module command, interfaces in the module will be ignored.
For example, if the definition of the module is:
module even_top (
input clk, reset, flush, flush_include_3rd,
output logic [127:0] result_forward_port[7],
stage_detect_interface.pipe even_stage_detect[9],
regFile_unit_interface.pipe to_reg_bus
);
where even_stage_detect and to_reg_bus are interfaces, the instantiate module will be like:
even_top u_even_top(
.clk(clk),
.reset(reset),
.flush(flush),
.flush_include_3rd(flush_include_3rd),
.result_forward_port(result_forward_port)
);