U.S.-Japan Collaborative Workshop: Accelerating IC Design [Phase II]

English | 日本語

This repository contains all material needed to participate in the tutorials at the U.S.-Japan Collaborative Workshop: Accelerating IC Design [Phase II]. Star or bookmark this repository for future reference.

Session Details

10:00 - 10:05 Opening Remark and Overview of the Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University
10:05 - 10:10 Welcome Remarks from the U.S. Consulate in Fukuoka
10:10 - 10:55 LLMs on ASICs, Greg Kielian/Kauna Lei, Google Research
11:00 - 11:45 Teaching Mixed-Signal Design Using Open-Source Tools, Boris Murmann, University of Hawaii
13:00 - 14:00 Photonic and Analog circuits with GDSFactory, Joaquin Matres/Troy Tamas, Google X/DoPlayDo, Inc.
14:15 - 15:45 ReaLLMASIC: Build your own Lightweight LLM, Gregory Kielian/Kauna Lei/Shiwei Liu/Mehdi Saligane, Google Research/University of Michigan
15:45 - 16:00 Conclusion, Mehdi Saligane, University of Michigan

10:00 - 10:05 Opening Remark and Overview of Day-2 Workshop, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University
10:05 - 10:50 Superconductor Computer Architecture: from Classical to Quantum, Ilkwon Byun, Kyushu University
10:50 - 11:35 Overview of new devices in the era of Beyond CMOS, Sadayuki Yoshitomi, Megachips
13:00 - 13:55 GLayout, Anhang Li/Mehdi Saligane, University of Michigan/University of Hawaii
13:55 - 14:50 (Tentative: XLS: High-Level Synthesis), Johan Euphrosine, Google
15:05 - 16:00 Pitfalls of Open-Source Chip Design Verification, Mitch Bailey, Efabless/ShuhariSystem
16:00 - 16:05 Conclusion and Overview of the phase-2 workshop activities, Mehdi Saligane/Koji Inoue, University of Michigan/Kyushu University

The live session requires registration to the workshop. The registration link can be found on the workshop website. (日本語)

This repository is licensed under the Apache License, Version 2.0. See LICENSE for the full license text.