mrisc32-a1
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mrisc32
A pipelined, in-order, scalar VHDL implementation of the MRISC32 ISA
With late forwarding of the addend, the MADD instruction would work as an MAC with zero latency for consecutive multiply+add operations such as: ``` madd r1, r2, r3 madd r1,...
It should be relatively easy to "pop bubbles" during a stall (i.e. don't propagate the stall signal to earlier stages if a stage is currently holding a bubble).
The ICache is more important than the DCache for most applications, and it is easier to implement. Having an ICache will leave the shared memory bus free for the data...
There are too many levels of MUX:ing going on, especially around the compare logic.
A memory store does not need the data operand until the 2nd execute pipeline stage. Being able to start the store instruction (to calculate the address) before the data operand...
The path to `o_is_vector_op_busy` (which in turn ends up controlling the stall signal & the IF memory interface) is fairly complex. Try to reduce the complexity.