VSRTL
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mortbopet
Visual Simulation of Register Transfer Logic
Implement all Primitive Operations in Firrtl [spec](https://github.com/freechipsproject/firrtl/blob/master/spec/spec.pdf) Then we can parse firrtl, dynamically build the circuit by components, then we can simulate the firrtl circuit. How do you think it?
Ie. Multiplexers should have their select port to be at either the top- or bottom of the component.
With #40 , it should be possible to partition the graph into subgraphs with no dependencies. These subgraphs are then valid to be executed in a separate thread. This task...
Currently, clocking the circuit is bound by the QEventLoop, limiting the circuit to be clocked at ~5ms intervals at a minimum. If faster simulations are desired, the circuit should be...
It should be possible to store and load a file for specifying the configuration of the graphical view. Serialized data should include: - Component positions - Component expansion state -...
Currently, the graphics view and netlist view have to manually synchronize selections. This is error prone and tedious to expand. A shared selection model should be implemented, to centralize selection...
Many places, unimplemented or unreachable states are marked by Q_ASSERT(false). Most of these should be replaced with Q_UNREACHABLE(), which is more fitting for the task.
This issue is related to removing some of the initial hardcoding, and moving it to a settings widget. The settings should be implemented through QSettings. **Drawing:** - Changing wire width...
It is annoying and verbose to type eg.: ``` INPUTPORT_W(acc, 32); ... return acc.value() == 0; ``` Comparison with integer literals is fairly safe, and should be implemented as an...
To have compile-time bit-width checking, propagation functions should be typed with a width paramter for instance ``` std::function m_propagationFunction; ``` would be transformed to ``` template std::function m_propagationFunction; ```