SRL/SLL/SRA violate spec by using all bits of rs2

[brakhane]

The ISA spec states:

SLL, SRL, and SRA perform logical left, logical right, and arithmetic right shifts on the value in register rs1 by the shift amount held in the lower 5 bits of register rs2.

The current implementation does not perform that implicit and 0x1f, so in the following program, x3 ends up containing zero instead of 0x7fffffff

li x1, 0xffffffff
li x2, 0x21
srl x3, x1, x2