Matthew Nicely comments

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                                            Matthew Nicely

Can't train in FP16 on Turing

cuDNN SDPA doesn't support Turing GPUs.

[FEA] Structured sparsity for convolution

Thanks for the request. This is something we've been thinking about but don't have the bandwidth to work on at the moment. Could you tell me more about your use...

[QST] What's the motivation of example 63?

https://docs.nvidia.com/cuda/cuda-c-programming-guide/index.html#programmatic-dependent-launch-and-synchronization

[QST] How do I get PTX from CuTE DSL kernels?

https://github.com/NVIDIA/cutlass/issues/2302#issuecomment-2886934868

[BUG] ElementC=void kernel reads non-void in `GemmDescription`

Yes.

Flash Attention 3 fp8 support 4090?

@hg0428 can you offer insight into why you need FA FP4 support? Have you tested the accuracy?

[FEA] [CuteDSL] Request for arm64 wheel

@tridao were working on it now! Will have an ETA soon

[FEA] [CuteDSL] Request for arm64 wheel

@IonThruster

`fp32` or even `fp64` support for cudnn flashattention

What other requirements would you have for FP32/FP64, such as head dim, seq_len, etc...

block_scale_quantize example

@Anerudhan for hardware restrictions. @JayL323 I'lol look into the example. Do you have particular configuration in mind?