Tim 'mithro' Ansell
Tim 'mithro' Ansell
@stefanor Is this done? Or do we just check for `\n\r` bits?
http://www.sphinx-doc.org/en/stable/config.html
Migen's config -> https://github.com/m-labs/migen/blob/master/doc/conf.py
@rohitk-singh - Can you show @stefanor ?
UART? ``` INFO:Xst:3231 - The small RAM will be implemented on LUTs in order to maximize performance and save block RAM resources. If you want to force its implementation on...
Something in controllerinjector_bankmachine? ``` INFO:Xst:3218 - HDL ADVISOR - The RAM will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block...
@enjoy-digital Do you have any ideas about the error > XXXX will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block...
@enjoy-digital Let me rephrase the question; Is the bank machine in the DDR controller is actually using an asynchronous read or is it a different feature that is causing the...
I moved your https://github.com/timvideos/litex-buildenv/wiki/building_hdmi2usb_gateware to https://github.com/timvideos/litex-buildenv/wiki/Building-HDMI2USB-Gateware and added some links to the it from other pages in the wiki. https://github.com/timvideos/litex-buildenv/wiki/Building-HDMI2USB-Gateware looks like a good start but could be expanded a...
Rohit - see https://github.com/timvideos/litex-buildenv/issues/157