Tim 'mithro' Ansell
Tim 'mithro' Ansell
@GCHQDeveloper560 - I haven't looked at your code yet but wanted to mention that @kgugala did some similar work here in https://github.com/SymbiFlow/fpga-tool-perf - https://github.com/SymbiFlow/fpga-tool-perf/pull/39/files#diff-d3e967d03ea41d0f7e921c5259e84d50R102-R183 - https://github.com/SymbiFlow/fpga-tool-perf/blob/master/vivado.py#L67-L131 @kgugala Discovered this really...
FYI - @hzeller
> @mithro what would be the goal of such an integration? Specify all source files in bazel description files, and use edalize to > > * call the EDA tools?...
FYI -- @acomodi @kgugala
Maybe the stuff at https://github.com/YosysHQ/yosys/pull/3138 could help?
@imphil - The very fact it is hard to get tool versions easily makes it a perfect thing to be part of edalize!
Have you seen https://github.com/hdl/bazel_rules_hdl ?
While Bazel has a lot of nice features, it is a very heavy dependency. I doubt it would be a good idea for FuseSoC to require it. However, (optional) FuseSoC...
I think there are two modes; * Using a Migen core inside a FuseSoC design. * Using a FuseSoC core inside a Migen design. While both can already be done,...
@cr1901 was working on this recently and even had a demo somewhere?