mirage-solo5

mirage-solo5 copied to clipboard

hannesm

samoht

This is small modification to support the aarch32 architecture by Solo5. Related pull requests can be found at https://github.com/Solo5/solo5/pull/470 and https://github.com/mirage/ocaml-freestanding/pull/78.

TImada

This is my current working state of the necessary modifications for PCIe support on Solo5. It also includes the stubs for [ixy.ml](https://github.com/ixy-languages/ixy.ml), as I couldn't figure out how to link...

bonkf

licensing

2

The opam file advertises `ISC` as license, but some files - e.g. main.ml - include a LGPL 2.1 with static linking exception header. In the meantime (June 2018, lwt 4.1.0,...

hannesm

Lwt.pause deadlock on spt

5

```ocaml open Lwt.Syntax module Hello (T : Mirage_time.S) = struct let f1c = ref 0 let f2c = ref 0 let rec f1 () = Logs.info (fun f -> f...

Firobe